=== 1 Overview
=== 2 Who does what
=== 3 The kbuild files
--- 3.1 Goal definitions
--- 3.2 Built-in object goals - obj-y
--- 3.3 Loadable module goals - obj-m
--- 3.4 Objects which export symbols
--- 3.5 Library file goals - lib-y
--- 3.6 Descending down in directories
--- 3.7 Compilation flags
--- 3.8 Command line dependency
--- 3.9 Dependency tracking
--- 3.10 Special Rules
--- 3.11 $(CC) support functions
=== 4 Host Program support
--- 4.1 Simple Host Program
--- 4.2 Composite Host Programs
--- 4.3 Defining shared libraries
--- 4.4 Using C++ for host programs
--- 4.5 Controlling compiler options for host programs
--- 4.6 When host programs are actually built
--- 4.7 Using hostprogs-$(CONFIG_FOO)
=== 5 Kbuild clean infrastructure
=== 6 Architecture Makefiles
--- 6.1 Set variables to tweak the build to the architecture
--- 6.2 Add prerequisites to archprepare:
--- 6.3 List directories to visit when descending
--- 6.4 Architecture-specific boot images
--- 6.5 Building non-kbuild targets
--- 6.6 Commands useful for building a boot image
--- 6.7 Custom kbuild commands
--- 6.8 Preprocessing linker scripts
=== 7 Kbuild syntax for exported headers
--- 7.1 header-y
--- 7.2 objhdr-y
--- 7.3 destination-y
--- 7.4 unifdef-y (deprecated)
=== 8 Kbuild Variables
=== 9 Makefile language
=== 10 Credits
=== 11 TODO
1.
Makefile the top Makefile. .config the kernel configuration file.arch/$(ARCH)/Makefile the arch Makefile.
scripts/Makefile.* common rules etc. for all kbuild Makefiles.
kbuild Makefiles there are about 500 of these.
arch Makefile with the name arch/$(ARCH)/Makefile
3.0
The preferred name for the kbuild files are 'Makefile'
but 'Kbuild' can be used and
if both a 'Makefile' and a 'Kbuild' file exists, then the 'Kbuild' file will be used.
3.1
Built-in object goals - obj-y
(如果要built-in kernel 就將object 加入 obj-y list
)
Loadable module goals - obj-m
(如果單純只是module 就將object 加入 obj-m list)
ibrary file goals - lib-y
list objects that will be included in a library, lib.a.
ibrary file goals - lib-m
lib-m will be included in lib.a.
Example:
obj-$(CONFIG_FOO) += foo.o
為了可以改變object的類別所以用變數$(CONFIG_xxxx) 代入m或y
3.2
The kbuild Makefile specifies object files for vmlinux in the $(obj-y) lists
Kbuild compiles all the $(obj-y) files.
It then calls "$(LD) -r" to merge these files into one built-in.o file.
built-in.o is later linked into vmlinux by the parent Makefile.
$(obj-y) list上的接下來都會被compiler,並且透過"$(LD) -r"去產生built-in.o
這些built-in.o會被連結進 vmlinux
圖中每個目錄下都有各自的 built-in.o
3.3
If a kernel module is built from several source files, you specify that you want to build a module in the same way as above.
module 可能包含很多個.o檔，最後產生.ko
Example:
#drivers/isdn/i4l/Makefile
obj-$(CONFIG_ISDN) += isdn.o
isdn-objs := isdn_net_lib.o isdn_v110.o isdn_common.o
Example:
#fs/ext2/Makefile
obj-$(CONFIG_EXT2_FS) += ext2.o
ext2-y := balloc.o bitmap.o
ext2-$(CONFIG_EXT2_FS_XATTR) += xattr.o
被包入的.o也可以透過變數改變，如果CONFIG_EXT2_FS_XATTR是y，則會被包入kernel
3.4 Objects which export symbols
No special notation is required in the makefiles for modules exporting symbols.
..... ???
3.5
ibrary file goals - lib-y
Objects that are listed in obj-y and additionally listed in lib-y will not be included in the library, since they will be accessible anyway.
All objects listed with lib-y are combined in a single library for that directory.
Example:
#arch/i386/lib/Makefile
lib-y := checksum.o delay.o
This will create a library lib.a based on checksum.o and delay.o.
For kbuild to actually recognize that there is a lib.a being built,
the directory shall be listed in libs-y.
Use of lib-y is normally restricted to lib/ and arch/*/lib.
資料夾內產生 lib.a檔，通常會限制在lib/ 或arch/*/lib. 資料夾
3.6 Descending down in directories
ext2 lives in a separate directory, and the Makefile present in fs/
tells kbuild to descend down using the following assignment.
Example:
#fs/Makefile
obj-$(CONFIG_EXT2_FS) += ext2/
如果添加目錄的方式，則會到下一層目錄執行下一層目錄的makefile
linux/drivers/scsi/Makefile
linux/Makefile
driver/ 依linux/Makefile 會產生 built-in.o
3.7
(全域變數)
ccflags-y, asflags-y and ldflags-y
Flags with the same behaviour were previously named:
EXTRA_CFLAGS, EXTRA_AFLAGS and EXTRA_LDFLAGS.
ccflags-y specifies options for compiling C files with $(CC).
Example:
# drivers/sound/emu10k1/Makefile
ccflags-y += -I$(obj)
ccflags-$(DEBUG) += -DEMU10K1_DEBUG
asflags-y is a similar string for per-directory options when compiling assembly language source.
Example:
#arch/x86_64/kernel/Makefile
asflags-y := -traditional
ldflags-y is a string for per-directory options to $(LD).
Example:
#arch/m68k/fpsp040/Makefile
ldflags-y := -x
(區域性，作用在subdir)
subdir-ccflags-y,
subdir-asflags-y
(索有子目錄都會套用)
The two flags listed above are similar to ccflags-y and as-falgs-y.
The difference is that the subdir- variants has effect for the kbuild
file where tey are present and all subdirectories.
Options specified using subdir-* are added to the commandline before
the options specified using the non-subdir variants.
Example:
subdir-ccflags-y := -Werror
(區域性，只作用在這個Makefile)
CFLAGS_$@ and AFLAGS_$@ only apply to commands in current kbuild makefile.
# drivers/scsi/Makefile
CFLAGS_aha152x.o = -DAHA152X_STAT -DAUTOCONF
CFLAGS_gdth.o = -DDEBUG_GDTH=2 -D__SERIAL__ -D__COM2__ \
-DGDTH_STATISTICS
CFLAGS_seagate.o = -DARBITRATE -DPARITY -DSEAGATE_USE_ASM
3.9 Dependency tracking
Kbuild tracks dependencies on the following:
1) All prerequisite files (both *.c and *.h)
2) CONFIG_ options used in all prerequisite files
3) Command-line used to compile target
Thus, if you change an option to $(CC) all affected files will
be re-compiled.
如果更動了，所有相依的檔案會重新compiler
(也就是不會整個重新都build，有改動才會)
3.10 Special Rules
A typical example is header files generated during the build process.
Another example are the architecture-specific Makefiles which need special rules to prepare boot images etc.
$(src)
$(src) is a relative path which points to the directory
where the Makefile is located. Always use $(src) when
referring to files located in the src tree.
$(obj)
$(obj) is a relative path which points to the directory
where the target is saved. Always use $(obj) when
referring to generated files.
Example:
#drivers/scsi/Makefile
$(obj)/53c8xx_d.h: $(src)/53c7,8xx.scr $(src)/script_asm.pl
$(CPP) -DCHIP=810 - < $< | ... $(src)/script_asm.pl
$(kecho)
echoing information to user in a rule is often a good practice
but when execution "make -s" one does not expect to see any output
except for warnings/errors.
To support this kbuild define $(kecho) which will echo out the
text following $(kecho) to stdout except if "make -s" is used.
Example:
#arch/blackfin/boot/Makefile
$(obj)/vmImage: $(obj)/vmlinux.gz
$(call if_changed,uimage)
@$(kecho) 'Kernel: $@ is ready'
3.11 $(CC) support functions
編譯可選用的功能
..
cc-option-yn
cc-option-yn is used to check if gcc supports a given option
and return 'y' if supported, otherwise 'n'.
Example:
#arch/ppc/Makefile
biarch := $(call cc-option-yn, -m32)
aflags-$(biarch) += -a32
cflags-$(biarch) += -m32
...
...
..
4 Host Program support
Kbuild supports building executables on the host for use during the compilation stage.
ex. compiler kernel 需要用到的工具
ex. compiler kernel 需要用到的工具
4.1
In some cases there is a need to compile and run a program on the
computer where the build is running.
The following line tells kbuild that the program bin2hex shall be
built on the build host.
Example:
hostprogs-y := bin2hex
Kbuild assumes in the above example that bin2hex is made from a single
c-source file named bin2hex.c located in the same directory as
the Makefile.
4.2
C Example:
#scripts/lxdialog/Makefile
hostprogs-y := lxdialog
lxdialog-objs := checklist.o lxdialog.o
Objects with extension .o are compiled from the corresponding .c files.
In the above example, checklist.c is compiled to checklist.o
and lxdialog.c is compiled to lxdialog.o.
Finally, the two .o files are linked to the executable, lxdialog.
Note: The syntax <executable>-y is not permitted for host-programs.
(要產生build時期用的執行檔 lxdialog 必須用hostprogs-y 而非 lxdialog-y)
kbuild offers support for host programs written in C++. This was
introduced solely to support kconfig, and is not recommended
for general use.
--- 4.3 Defining shared libraries
Objects with extension .so are considered shared libraries, and
will be compiled as position independent objects.
Kbuild provides support for shared libraries, but the usage
shall be restricted.
In the following example the libkconfig.so shared library is used
to link the executable conf.
Example:
#scripts/kconfig/Makefile
hostprogs-y := conf
conf-objs := conf.o libkconfig.so
libkconfig-objs := expr.o type.o
Shared libraries always require a corresponding -objs line,
and in the example above the shared library libkconfig is composed by the two objects
expr.o and type.o.
expr.o and type.o will be built as position independent code and
linked as a shared library libkconfig.so.
C++ is not supported for shared libraries.
(compiler工具時也可以使用lib，但使用上必須很小心，例如工具在compiler PC 64bit上使用,而產生的kernel是32 bit system)
4.4 Using C++ for host programs
C++ Example:
#scripts/kconfig/Makefile
hostprogs-y := qconf
qconf-cxxobjs := qconf.o
4.5 Controlling compiler options for host programs
When compiling host programs, it is possible to set specific flags.
The programs will always be compiled utilising $(HOSTCC) passed
the options specified in $(HOSTCFLAGS).
To set flags that will take effect for all host programs created
in that Makefile, use the variable HOST_EXTRACFLAGS.
Example:
#scripts/lxdialog/Makefile
HOST_EXTRACFLAGS += -I/usr/include/ncurses
To set specific flags for a single file the following construction
is used:
Example:
#arch/ppc64/boot/Makefile
HOSTCFLAGS_piggyback.o := -DKERNELBASE=$(KERNELBASE)
It is also possible to specify additional options to the linker.
Example:
#scripts/kconfig/Makefile
HOSTLOADLIBES_qconf := -L$(QTDIR)/lib
When linking qconf, it will be passed the extra option
"-L$(QTDIR)/lib".
4.6 When host programs are actually built
Example: (典型的工具製作和使用)
#drivers/pci/Makefile
hostprogs-y := gen-devlist
$(obj)/devlist.h: $(src)/pci.ids $(obj)/gen-devlist
( cd $(obj); ./gen-devlist ) < $<
The target $(obj)/devlist.h will not be built before
$(obj)/gen-devlist is updated. Note that references to
the host programs in special rules must be prefixed with $(obj).
(2) Use $(always)
When there is no suitable special rule, and the host program
shall be built when a makefile is entered, the $(always)
variable shall be used.
Example:
#scripts/lxdialog/Makefile
hostprogs-y := lxdialog
always := $(hostprogs-y)
4.7 Using hostprogs-$(CONFIG_FOO)
A typical pattern in a Kbuild file looks like this:
Example:
#scripts/Makefile
hostprogs-$(CONFIG_KALLSYMS) += kallsyms
Kbuild knows about both 'y' for built-in and 'm' for module.
So if a config symbol evaluate to 'm', kbuild will still build
the binary. In other words, Kbuild handles hostprogs-m exactly
like hostprogs-y. But only hostprogs-y is recommended to be used
when no CONFIG symbols are involved.
5. Kbuild clean infrastructure
"make clean" deletes most generated files in the obj tree where the kernel
is compiled. This includes generated files such as host programs.
Additional files can be specified in kbuild makefiles by use of $(clean-files).
雖然make clean可以刪除大部分編譯出來的檔案，但是有些工具產生的檔案
必須另外添加刪除，例如hostprogs產生的 .h
Example:
#drivers/pci/Makefile
clean-files := devlist.h classlist.h
Example: (將debian/* 刪除 ，會從子目錄開始刪除)
#scripts/package/Makefile
clean-dirs := $(objtree)/debian/
Example:(將compressed/* 刪除 ，會從子目錄開始刪除)
#arch/i386/boot/Makefile
subdir- := compressed/
Example:
#arch/i386/Makefile
archclean:
$(Q)$(MAKE) $(clean)=arch/i386/boot
When "make clean" is executed, make will descend down in arch/i386/boot,
and clean as usual. The Makefile located in arch/i386/boot/ may use
the subdir- trick to descend further down.
Note 1: arch/$(ARCH)/Makefile cannot use "subdir-", because that file is
included in the top level makefile, and the kbuild infrastructure
is not operational at that point.
Note 2: All directories listed in core-y, libs-y, drivers-y and net-y will
be visited during "make clean".
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